• As chip designs grow more complex and software-driven, verification teams are running more engines, larger regressions, and deeper analyses than ever before—yet achieving confidence and closure often feels harder, not easier.

    In this Siemens EDA–sponsored luncheon panel, industry experts and practitioners discuss how verification is evolving as designs scale beyond the practical limits of any single engine. Panelists will share the challenges of coordinating simulation, formal, emulation, prototyping, and verification data, along with the pragmatic approaches teams use today—combining advanced commercial solutions with in-house workflows layered on existing platforms.

    Looking ahead, the discussion explores the shift from raw engine output to intelligence, including the role of AI technologies and emerging agentic approaches. The panel will examine how these capabilities are being explored—and in some cases applied—to interpret results, prioritize risk, and help verification engineers sustain confidence as scale continues to increase.

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    • Harry-Professional-Photo.jpg
      Harry Foster
    • Darron-May-5x7-Hi.jpg
      Darron May

      Siemens DVT

    • Vijay-Chobisa-HS-2048x1348-1911776991.jpg
      Vijay Chobisa

      Siemens HAV

    • apurva portrait 26.jpg
      Apurva Brahmbhatt

      Sr. Director – DCE Connectivity, Marvell

    • IMG_7040.jpeg
      Susheel Tadikonda

      VP & Head of Engineering, Silicon IP, Rambus