Richard Weber, Fellow, Director of Engineering, Arteris; Anupam Bakshi, CEO, Agnisys
This workshop explains the data model underlying the IP-XACT standard. This SoC data model unifies logical and physical connectivity as well as memory map and registers which enables the standard to be used as a single source of truth to automate large parts of SoC front-end design and verification flows.
The workshop will address IP-XACT concepts that are relevant to understand the overall SoC data model such as:
Components
Design and Design Configurations
Bus and Abstraction Definition
Component Memory Maps and Registers
Component Address Spaces and Bus Interface Bridges
Type Definitions