Richard Weber, Fellow, Director of Engineering, Arteris; Anupam Bakshi, CEO, Agnisys
This workshop explains the data model underlying the IP-XACT standard. This SoC data model unifies logical and physical connectivity as well as memory map and registers which enables the standard to be used as a single source of truth to automate large parts of SoC front-end design and verification flows.
The workshop will address IP-XACT concepts that are relevant to understand the overall SoC data model such as:
Components
Design and Design Configurations
Bus and Abstraction Definition
Component Memory Maps and Registers
Component Address Spaces and Bus Interface Bridges
Type Definitions
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.
