The semiconductor industry faces relentless pressure to shorten design cycles, improve quality, and manage escalating complexity. Traditional EDA tools have made remarkable progress, yet verification still consumes the majority of project schedules and resources. Recent breakthroughs in large language models and agentic AI present a transformative opportunity: autonomous, task-oriented agents that can collaborate with engineers in design and verification workflows.

This workshop explores the promise and limitations of AI agents applied to RTL design, debug, and verification. We will demonstrate how agentic systems can generate UVM testbenches, accelerate coverage closure, and automate tedious debugging tasks, all while integrating seamlessly with existing toolchains through standard EDA workflows. At the same time, we will examine the critical challenges that remain: ensuring correctness and determinism, handling corner cases, and scaling performance across large design teams.

Participants will gain a grounded understanding of where AI agents add real value today, what open problems the community must address, and how engineers can adopt these tools responsibly. Through case studies and interactive discussion, we will highlight early successes, industry feedback, and research directions that could reshape how verification is performed in the next decade.

Whether you are a verification engineer, design engineer, or decision-maker, this session will help you separate hype from reality and envision a future where AI agents become trusted fellow engineers in the chip design process.