The rapid growth in semiconductor design activity is projected to increase in the coming years, however, RTL design and verification remains a significant challenge in semiconductor development. While emulation is widely adopted to accelerate verification, today, most emulation technologies cater to the needs of large-scale ‘billion-gate’ class designs.

Many design teams across various organizations create IP or small-scale yet mission-critical ASIC/SoC designs and strive to leverage emulation. Unfortunately, existing emulation solutions are often inaccessible to these teams due to constraints such as limited capital budgets, low priority in resource allocation, or lack of data center infrastructure.

To lower the barrier of adoption, Cadence introduced the Dynamic Duo System Studio, comprising the Palladium Z3 System Studio and the Protium X3 System Studio. The Palladium Z3 System Studio is a standalone emulation appliance tailored to emulate designs up to 128 million gates, with software and tool flows compatible with the enterprise-scale Palladium Z3 system.

In this session, we intend to present the benefits and features of the Palladium Z3 System Studio-- a leading-edge emulation appliance that significantly lowers the adoption barrier for design and verification teams, enabling them to accelerate hardware/software co-verification workloads via emulation.

We also intend to share case studies from companies specializing in AI chip development and other mission-critical applications. These case studies will demonstrate how design teams achieved multi-thousand-fold performance improvements over simulation, shortened verification cycles, and accelerated software bring-up by several months through the adoption of System Studio into their workflows.