High-Level Synthesis (HLS) is an established design methodology that raises the abstraction level for design and verification. Verification at the abstract level runs much faster than RTL level simulations. But abstract simulations cannot completely verify the implementation, as it omits certain RTL details. For a complete verification, some verification must be performed at the RTL level.

This talk will describe a design flow that enables FPGA prototype verification of an HLS synthesized module using an Amazon AWS F2 instance as the FPGA prototyping system. AWS F2 instances provide 8 AMD Virtex UltraScale+ HBM VU47P FPGAs on a PCIe card, with DPI and C++ interfaces. The HLS synthesized RTL module is run through the Xilinx tools to program the FPGAs. The HLS C++ testbench, and its associated results checking and coverage, can be reused to with the module loaded into the FPGAs. This enables the proven testbench environment from the HLS flow to be used with a full RTL implementation of the module. Bus interfaces, memories, and interrupt logic can all be modeled and verified at the RTL level, these structures are often abstracted away in High-Level Verification flows. FPGA prototyping can be an ideal complement to High-Level Verification in an HLS design flow. Using cloud-based FPGA instances on AWS eliminates the need for hardware acquisition and management, and can scale up and down as needed based on verification demands.