Georgios Passas, Arteris; Aiyush Aggarwal, Agnisys; Freddy Nunez, Agnisys; Thomas Burg, STMicroelectronics; Richard Weber, Arteris
As System-on-Chip (SoC) designs grow in scale and complexity, integration teams face significant challenges in managing registers, memory maps, IP packaging, and verification collateral. Traditional methods based on spreadsheets or proprietary formats often result in inconsistencies, delays, and costly rework.
IEEE 1685-2022 (IP-XACT), developed by Accellera, provides a vendor-neutral framework to describe, package, and integrate IP. The 2022 revision introduces an updated schema, richer register and memory map support, and enhanced mechanisms for capturing hierarchy and connectivity. These improvements enable consistent design data exchange across design, verification, and software teams, while supporting greater automation and reuse.
This training workshop provides participants with a practical understanding of IP- XACT 2022 and how to apply it in real SoC projects.
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. We are composed of a broad range of members that fully support the work of our technical committee to develop technology standards that are balanced, open, and benefit the worldwide electronics industry. Leading companies and semiconductor manufacturers around the world are using our electronic design automation (EDA) and intellectual property (IP) standards in a wide range of projects in numerous application areas to develop consumer, mobile, wireless, automotive, and other “smart” electronic devices. Through an ongoing partnership with the IEEE, standards and technical implementations developed by Accellera Systems Initiative are contributed to the IEEE for formal standardization and ongoing governance.
