Tuesday, March 5, 2024

  • Seokho Lee, FuriosaAI; Youngsik Kim, FuriosaAI; Suhyung Kim, FuriosaAI; Jeong Ki Lee, FuriosaAI; Wooyoung Choe, FuriosaAI; Minho Kim, FuriosaAI

    Over the past few years, there has been a growing trend of using Python for design verification instead of traditional hardware verification languages such as SystemVerilog. However, existing Python verification frameworks focus on driving and monitoring signals or solving random constraints, but lack coverage features which makes it hard to achieve functional coverage closure. This paper proposes a Python environment for enabling functional coverage closure. This environment fully utilizes rich features of SystemVerilog functional coverage as well as leverages existing tools for easier coverage analysis.

  • Robert Kunzelmann, Infineon Technologies AG, Technical University of Munich; Aishwarya Sridhar, Infineon Technologies AG; Daniel Gerl, Infineon Technologies AG, Technical University of Munich; Lakshmi Vidhath Boga, Infineon Technologies AG; Wolfgang Ecker, Infineon Technologies AG, Technical University of Munich

    Function set modeling is a specification methodology striving for the unified description of general hardware systems. Based on the Instruction Set Architecture (ISA) of processors, function set modeling specifies systems exclusively by their executable functions and the relevant system state. While this methodology has been used in formal verification and behavioral modeling, the abstraction gap between system-level function models and design implementation limits its significance. We use traces, time-annotated representations of functions, to additionally model architecture parameters. Hierarchical State Machines (HSMs) are leveraged as a notation to capture the refined and conditional execution of the underlying function set. Moreover, we show the transformation of traces into formal assertion properties spanning over fixed-length intervals. The extracted interval set jointly verifies the complete behavior captured by the traces, thereby checking the functional and temporal correctness of the Design Under Verification (DUV).

  • Jikjoo Lee, Samsung Electronics, Memory Division South Korea; Kihyun Park, Samsung Electronics, Memory Division South Korea; Tony Gladvin George, Samsung Electronics, Memory Division South Korea; Dongkun An, Samsung Electronics, Memory Division South Korea; Wooseong Cheong, Samsung Electronics, Memory Division South Korea; Byungchul Yoo, Samsung Electronics, Memory Division South Korea

    In the context of hardware design verification, defining function coverage accurately in SystemVerilog remains a challenge, largely due to human errors leading to "missing coverbins". This paper introduces a methodology aimed at enhancing function coverage by identifying these overlooked bins. By treating coverbins as a SystemVerilog queue and employing an "waive function", this approach provides verification engineers a mechanism to efficiently determine whether sampled cover point already accounted for in the coverage. Experimental validation, involving the CacheManager in an SSD Controller, underscored the method's efficacy, with results revealing a significant 16.4% improvement in functional coverage. Thus, the proposed method not only rectifies human-induced inaccuracies but also improves the overall robustness of hardware verification.

  • Yash Phogat, Arm Inc.; Patrick Hamilton, Arm Inc.

    Verifying a complex hardware design is a compute-intensive task. Design verification often uses a constrained random approach to simulate tests using random stimuli. However, due to the random nature of this approach, efficiency diminishes over time, i.e., as the hardware design becomes stable, we find large amounts of wasted compute cycles in running tests that always pass. For a given regression on a stable design, while the passing cycles may be useful for coverage, they certainly do not contribute to finding newer bugs. Using Machine Learning (ML) we model the tests history to build classification models that filter the tests with high likelihood of passing. To do this, the machine learns to identify(model) the parts of the test input stimulus which show high correlation to the fail/pass label. By applying the learnt model to a new test input stimulus, we obtain a subset of tests that are useful to simulate. Running this smaller set of tests on simulators will cut down the test regression size. The saved compute can either be repurposed or translated to savings in verification costs.