The program is tentative and may undergo revisions.  Registration begins 30 minutes before each day's first session. 

Download the PDF Program

Magnolia Grand Ballroom C Grand Ballroom D Grand Ballroom EFGH
9:00–10:30 System Validation - It's the Protocol Stupid (Part 1)
Synopsys
Liberating Functional Verification from Boolean Shackles
Real Intent
Portable Stimulus Modeling Patterns (Practical Tips for Adopting PSS)
Accellera
Venue Set Up
10:30–11:00 Coffee Break
(Grand Ballroom ABCD Foyer)
11:00–12:30 System Validation - It's the Protocol Stupid (Part 2)
Synopsys
Property Generator: Simple Generation of Formal Assertion IP
Sponsor
SystemC – What's New? What's Next?
Accellera
12:30–13:30 Sponsored Lunch
From Failing Test to Fix: Agentic Root Cause Analysis for Modern Verification
(Grand Ballroom AB)

ChipAgents AI
Exhibitor Set Up
13:30–15:00 AI Agents for Design and Verification: Opportunities and Challenges
ChipAgents AI
AI Meets Formal: Practical Applications from Industry Leaders
Synopsys
TvastaaVP: An Agentic AI Approach to SystemC (Part 1)
Vayavya
15:00–15:30 Coffee Break
(Grand Ballroom ABCD Foyer)
15:30–17:00 ChipAgents in Practice: Lessons from One Year of Agentic AI EDA Deployment
ChipAgents AI
Automate the Pain Away: HW/SW Interface Design Methodology
Sponsor
TvastaaVP: An Agentic AI Approach to SystemC (Part 2)
Vayavya
17:00–18:00 Welcome Reception Sponsored by Accellera Systems Initiative
Exhibit Hall Open to All Attendees & Exhibit Staff
(Grand Ballroom EFGH/Exhibit Hall)

Accellera
Magnolia Grand Ballroom C Grand Ballroom D Grand Ballroom EFGH
8:30–9:00 Opening Session
(Grand Ballroom C)
9:00–10:30 1 Accelerating Coverage 2 Functional Safety 3 Coverage in Memory Design
10:30–11:00 Coffee Break
(Grand Ballroom ABCD Foyer)
10:30–12:00 Poster Session
(Grand Ballroom ABCD Foyer)
12:00–13:00 Sponsored Lunch
From Engines to Intelligence: Managing Verification at Massive Scale
(Grand Ballroom AB)

Siemens
Exhibit Hall Open
13:00–14:00 Industry Keynote: Beyond Bigger Designs: Rethinking Verification for the Era of Convergence
(Grand Ballroom CD)
Siemens
14:00–14:30 Coffee Break
(Grand Ballroom EFGH/Exhibit Hall)
14:30–16:30 4 Formal Automation 5 Security in Design & Verification 6 Digital Twin / Emulation Acceleration
16:30–18:00 Reception
(Grand Ballroom EFGH/Exhibit Hall)
Magnolia Grand Ballroom C Grand Ballroom D Grand Ballroom EFGH
8:30–9:30 Panel
(Grand Ballroom CD)
9:30–10:00 Coffee Break
(Grand Ballroom ABCD Foyer)
10:00–12:00 7 Formal Verification Innovations 8 Automating Verification Insight 9 UVM Practices
12:00–13:00 Sponsored Lunch
Bridging Minds and Machines: How AI is Transforming the Future of Design Verification
(Grand Ballroom AB)

Cadence
Exhibit Hall Open
13:00–14:00 Invited Keynote: From Pixels to Tokens: Chip Design and Verification in the Era of AI
(Grand Ballroom CD)
Keynote Speaker
14:00–15:00 Poster Ninja Session
(Grand Ballroom CD)
15:00–15:30 Coffee Break
(Grand Ballroom EFGH/Exhibit Hall)
15:30–17:00 10 Regression Management 11 Tightening Verification Closure 12 Python Integration
17:00–18:30 Reception & Best Paper Presentation
(Grand Ballroom EFGH/Exhibit Hall)

Please note that lunch sessions are reserved exclusively for all-access pass holders. Please be aware that seating for lunch sessions is limited and available on a first-come, first-served basis for All-Access pass holders only.

2026 exhibitor map.
2026 venue map.