The program is tentative and may undergo revisions.  Registration begins 30 minutes before each day's first session. 

Learn More about the Workshops & Tutorials Learn More about the Technical Sessions
Monterey Carmel Oak Fir Bayshore Ballroom
9:00–10:30 Modernizing the Hardware / Software Interface - Life beyond spreadsheets. How to bring your SoC register design into the 21st Century
Sponsor 		Accelerating Functional Verification with Machine Learning
Sponsor 		Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent
Accellera 		Venue Set Up
10:30–11:00 Coffee Break
(Gateway Foyer)
11:00–12:30 Accelerating Design & Verification with AI Agents
ChipAgents AI 		Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration
Accellera 		Emulation Driven Power Estimation for Real World Application
Cadence
12:30–13:30 Lunch
(Pine Cedar)
Accellera 		Exhibitor Set Up
13:30–15:00 PSS case studies in real-life projects
Cadence 		Step Function Leaps in RTL Functional Verification Powered by AI/ML Innovations
Sponsor 		Moving Application-level Power Optimization to Pre-silicon with Advanced Hybrid Emulation and Power Exploration Technologies
Synopsys
15:00–15:30 Coffee Break
(Gateway Foyer)
15:30–17:00 PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More
Accellera 		Complex Verification Example: RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC platforms
Sponsor 		Power Dynamics: Shaping the future of the data centric era
Sponsor
17:00–18:00 Welcome Reception
(Bayshore Ballroom)
Monterey Carmel Oak Fir Bayshore Ballroom
8:30–9:00 Opening Session
(Oak)
9:00–11:00 Session 1: Low Power UPF Session 2: Functional Safety Session 3: AI & ML in Verification
11:00–11:30 Coffee Break
(Gateway Foyer)
11:00–12:30 Poster Session
(Gateway Foyer)
12:30–13:30 Lunch
2024 Verification Trends Unveiled: Challenges, Surprises, and Siemens' Solutions
(Pine Cedar)
Siemens
13:30–14:30 Industry Keynote: AI Factories Drive Re-invention of Chip Design, Verification, and Optimization
(Oak/Fir)
Synopsys 		Exhibit Hall Open
14:30–15:00 Coffee Break
(Gateway Foyer)
15:00–17:00 Session 4: Portable Stimulus Session 5: AI & ML Coverage Closure Session 6: Regression Management
17:00–18:00 Reception
(Bayshore Ballroom)
Monterey Carmel Oak Fir Bayshore Ballroom
9:00–10:00 Panel: Are AI Chips Harder to Verify?
(Oak/Fir)
10:00–10:30 Coffee Break
(Gateway Foyer)
10:30–12:00 Session 7: Formal Verification Session 8: UVM in Practice Session 9: Coverage Modeling
12:00–13:00 Lunch - 2026 Announcement
(Pine Cedar)
13:00–14:00 Invited Keynote: The Role of EDA in U.S. Economic Security
(Oak/Fir) 		Exhibit Hall Open
14:00–15:00 Poster Ninja
(Oak/Fir)
15:00–15:30 Coffee Break
(Gateway Foyer)
15:30–17:00 Session 10: Verification IP Session 11: Testbench Generation Session 12: Analog/Digital Mixed Signal
17:00–18:30 Reception & Best Paper Presentation
(Bayshore Ballroom)
Cascade Donner Siskiyou
9:00–10:30 Next-Gen Verification Technologies for Processor-Based Systems
Synopsys 		Beyond Integers and Floating Point – Designing and Verifying with Alternate Number Representations
Sponsor 		SoC development automation using IP-XACT 1685-2022 standard
Accellera
10:30–11:00 Coffee Break
(Bayshore Foyer)
11:00–12:30 Next-Gen Verification Technologies for Processor-Based Systems
Synopsys 		Comprehensive Glitch Signoff – Learnings and experiences from industry use cases
Sponsor 		CDC/RDC Interchange Format Standard
Accellera
Speaker Resources and Guidelines Sponsor & Exhibitor Resources
2025 exhibitor layout.